1. Field of the Invention
The present invention relates to a semiconductor device having a heterojunction interface.
2. Description of the Related Art
Conventionally, a semiconductor device disclosed in Japanese Patent Application Laid-open No. 2003-318398 has been known. According to the semiconductor device, an N−-type polycrystalline silicon region is formed to contact one main surface of a semiconductor body including an N−-type silicon carbide epitaxial region on an N+-type silicon carbide substrate. A heterojunction interface is formed between the epitaxial region and the polycrystalline silicon region. Adjacently to the heterojunction interface, a gate electrode is formed via a gate insulating film. The polycrystalline silicon region is connected to a source electrode, and a bottom surface of the silicon carbide substrate is formed thereon with a drain electrode.
When a circuit is configured by arranging the semiconductor device in plural and in parallel, polycrystalline silicon regions of adjacent semiconductor devices are arranged separate with each other. Therefore, a level difference of the heterojunction interface is generated at the end of the heterojunction interface. As a result, when a reverse bias voltage is applied such as at the time of interruption, a leakage current concentration occurs in a region where the level difference is generated as compared to the other heterojunction interface region. Thus, there is a problem that an interruption characteristic is decreased as a semiconductor device.
The present invention has been achieved to solve the problem of the related art, and an object of the present invention is to provide a semiconductor device having a high interruption characteristic.